The present invention relates to a semiconductor memory device employing an error checking and correcting (ECC) circuit, and more particularly to a multi-ECC circuit embedded in a semiconductor memory device having a plurality of sub memory cell arrays.
As the packing density of semiconductor memory devices increases, bit failures or syndrome bits due to defective manufacturing steps or electrical stress surges can significantly reduce yield and reliability of the semiconductor memory device.
In nonvolatile memory devices, e.g., electrically erasable and programmable read only memory (EEPROM) or mask ROM which require high reliability, use of the ECC circuitry is a standard practice. Although ECC circuitry creates troubles, such as an increase of the chip size due to added parity cells and speed delay due to correction circuits, the increased reliability and yield compensate for these difficulties.
In particular, redundancy is difficult in a highly integrated ROM device, so ECC circuits enhance the yield and reliability.
ECC circuits generally work as follows. During an input operation, corresponding parity bits are generated and then both the input data and the parity bits are stored. During an output operation, the stored data and the corresponding parity bits are compared with each other, thereby detecting and correcting any error.
The number of the parity bits required varies according to the number of data bits. this number is determined in accordance with Hamming code, which is attained by: EQU 2.sup.k .ltoreq.m+k+1
where "m" denotes the number of data bits and "k" denotes number of parity bits. Therefore, according to the above equation, when the number of data bits is eight, the number of equation parity bits is four. Similarly, when the number of data bits is sixteen, the number of required parity bits is five.
A block diagram of a conventional semiconductor memory device having an ECC circuit for 128 bits is shown in FIG. 1. The number of parity bits is eight. The semiconductor memory device shown in FIG. 1 has a memory cell array 10A, sense amplifier group 20A for sensing data of the memory cell array 10A, latch circuit 30A for latching the output of the sense amplifier group 20A, an ECC circuit 40A for repairing a syndrome bit, an output decoder 50A for sequentially accessing the 128 bits by 16 bits by means of pre-decoding signals SAD0-SAD7 generated from a pre-decoder 80A, and a data output buffer 60A for providing output data by 16 bits to an output pad 70A.
In a page mode data access operation of the semiconductor memory device shown in FIG. 1, the data of 128 bits is sequentially output 16 bits at a time after passing the sense amplifier group 20A, the latch circuit 30A and the ECC circuit 40A, so that the data access can be performed in high speed. However, devices which operate also in a normal mode data access operation, since the sense amplifier group 20A, the latch circuit 30A and ECC circuit 40A are also all simultaneously activated. Thus, power dissipation is the same as during page mode operation, although these devices will not operate in a page mode.